Don't Use the Page Number, but a Pointer to It

Most newly announced high performance microprocessors support 64-bit virtual addresses and the width of physical addresses is also growing. As a result, the size of the address tags in the L1 cache is increasing. The impact of on chip area is particularly dramatic when small block sizes are used. At the same time, the performance of high performance microprocessors depends more and more on the accuracy of branch prediction and for reasons similar to those in the case of caches the size of the Branch Target Buuer is also increasing linearly with the address width. In this paper, we apply the simple principle stated in the title for limitingthe tag size of on-chip caches. In the resulting indirect-tagged cache, the duplication of the page number in processors (in TLB and in cache tags) is removed. The tag check is then simpliied and the tag cost does not depend on the address width. Applying the same principle to Branch Target Buuers, we propose the Reduced Branch Target Buuer. The storage size in a Reduced Branch Target Buuer does not depend on the address width and is dramatically smaller than the size of the conventional implementation of a Branch Target Buuer. all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for proot or commercial advantage and that new copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior speciic permission and/or a fee. Request Permissions from Publications Dept, ACM Inc., Fax +1 (212) 869-0481, or [email protected].